CS 231

Assembly Language and Digital Circuits

Spring 2004 Syllabus

 

Instructor                :                Kayhan Erciyes
Email                      :               kerciyes@csusm.edu
Phone                     :               (760) 750-8015
Lectures                  :               TR 1:00-2:15, LIB 1108
Labs                       :               TR 2:30-3:45  SCI 2206
Office Hours           :               TR 16:00-17:00 SCI 2227
Lab Instructor          :               Sahar Mosleh, saharmosleh@yahoo.ca
Prerequisites            :               CS 111
Emergency Contact :               Jo Ann Espinoza at 750-4118
                                         
1. Description

This course is an introduction to Assembly Programming and Digital Circuits. As its name suggests, it consists of these two distinct but overlapping components. In the first part of CS 231, we review the assembly language constructs using MIPS. MIPS is a Reduced Instruction Set Computer (RISC)  assembly language which means it can be mapped onto the hardware conveniently, unlike the other Complex Instruction Set Computer (CISC) assembly languages. It has also fewer instructions resulting in few more instructions to do the same thing with respect to a CISC architecture language. After the first part is over, you should gain the following skills:

-          A thorough understanding of the Instruction set Architecture (ISA) concepts

-          Fluency in interpreting various data structure formats

-          Ability to write MIPS code for various problems involving decisions, loops  

-          Understanding of procedure calling, its conventions using MIPS

-          Linking and loading concepts using MIPS example

In the second part, we review the basic hardware components, starting from the gate level. We learn how to design, meaning to build a circuit for a given function using simplification methods such as Karnaugh Maps. Then, we move on to larger circuits such as decoders and multiplexers. The second part has a second section called the sequential circuits. In this case, we review the basic components of the memory, learn how to build circuits with memory such as counters etc. Finally, we look at the Finite State Machines, which are the basis of the computer hardware among other things, how to analyze and design them. The ultimate goal of the second part of the course is to be able to understand the design of a simple processor. We conclude by reviewing MIPS hardware, showing the operation of various MIPS instructions and hopefully two worlds unite. After this part is over, you should gain the following skills:

-          Realization of a function by a digital circuit using any gate combination

-          Simplification of logical functions using Karnaugh Maps

-          Function realization by decoders, multiplexers

-          Understanding the operation of SR, D, JK, T flip flops

-          Analyzing the response of sequential circuits to any given input waveform

-          Building sequential circuits such as registers, counters

-          Analysis and design of Finite State Machines

-          Analysis of a simple processor and the MIPS processor

2. Text Book

Computer Organization and Design, The Hardware/Software Interface, D.Patterson and J.Hennesy, Morgan Kaufmann, 1997

            Reference Book:

            Digital Design, 3rd Edition, Morris Mano, Prentice-Hall

3. Lecture Notes :

There will be lecture notes as slides posted on the homepage of the course. The notes are self contained. In most cases, they are your fundamental resource. Some of the material in the lecture notes does not exist in either of the books and you are responsible with whatever is covered in the class based on the lecture notes. They will be posted latest before every lecture they are reviewed. It is always useful to take some notes as the lecture progresses as it is almost impossible to put everything in the notes. My notes are based on a similar UCB course with some modifications.

4. Topics:

            Assembly Language:

1.       MIPS;  Introduction, SPIM Simulator, MIPS instructions,

2.       Data Representations, arithmetic instructions

3.       Decision Making;  Branches, jumps, loops

4.       Procedure Calls ; Passing parameters, conventions

5.       Linking and Loading using MIPS

            Digital Circuits

1.       Boolean Algebra, gates

2.       Realization of functions, simplification using K-Maps

3.       Encoders, decoders, multiplexers, arithmetic circuits

4.       Sequential circuits; Latches and Flip flops

5.        Registers and Counters

6.       Finite State Machines; analysis and design

7.       Design of a simple processor and the MIPS processor

5. Assignments:

There will be 5 assignments. You should hand these in hardcopy and in the class or in my office mailbox by the due dates.  Important announcements (e.g. changes in due dates) can be made in the lectures. Therefore, your attendance is required and is very important.

 6. Labs :

The lab is provided to help you develop your hands-on skills in assembly language and circuit design. You are required to do the lab and hand in your lab work (source code and output) to the lab instructor. For all lab related problems, contact your lab instructor. The lab instructor cannot assist you unless you have the notes and assignment sheets next to your computer.

7. Exams:

The midterm will cover the first part of the course. The final  will concentrate on the second half, but there will  be some questions related to the first part. Both exams are open books, open notes.

8. Cheating, Plagiarism, etc.:

You may discuss the solution of a problem with other students, but if you end up with a similar solution out of many for a given problem, you should cite your peers. Do not copy others’ assignments or labs. The more you rely on the others to write or correct your programs, assignments, the worse you will do on the exams and later courses. Any copying of programs and their parts will be penalized as Plagiarism according to the university policy. You may not submit identical or nearly identical work. All parties involved will receive a zero score for the lab, assignment or the exam.

9.  Incompleteness :

Please refer to the CS program policy about Incompletes posted on our Web page. Incompletes apply only to "emergency" cases.

10. Grading:

1.       Assignments     25 %

2.       Labs                 35 %

3.       Midterm            15 %

4.       Final                 25 %

This is an absolute scale. You can guarantee yourself a  particular grade by attaining the appropriate overall percentage.

11. Checking Grades:

For any complaints related to the grading of labs, you should see your lab instructor. For any complaints related to the grading of exams and assignments contact me.

12.  CS 231 Spring 2004 Tentative Lecture Schedule

 

Date

Topic

Reading

Assigns

Notes (set)

1/20

Introduction

PH- Ch1

 

 MIPS1

1/22

C., MIPs and SPIM

PH-Ch3, App.A

 

 MIPS2

1/27

 ISA sand MIPS

PH-Ch4.1-4.3,4.8

A1 out

MIPS2-3

1/29

 Data Representations

PH-Ch4; M-Ch1

 

MIPS4

2/3

MIPS Instructions

PH-AppA

 

MIPS5

2/5

Decision Making

PH-Ch3, AppA

 

MIPS7

2/10

Jump and Branch

PH-Ch3, AppA

A2 out

MIPS7

2/12

Loops, Arrays

PH-Ch3,AppA

 A1 due

MIPS7

2/17

Arithmetic Instructions

PH-Ch3, AppA

 

MIPS8

2/19

Procedure Calls I

PH-Ch3

 

MIPS9

2/24

Procedure Calls II

PH-Ch3-Ch4

A2 due,A3 out

MIPS9

2/26

Procedure Calls III

PH-Ch.3,AppA

 

MIPS10

3/2

Linking and Loading

PH-Ch.4

 

MIPS11

3/4

MIPS Wrap-up

 

 

MIPS12

3/9

Midterm Review

 

A3 due

 

3/11

MIDTERM (in class)

 

 

 

3/16

Boolean Algebra

M-Ch2, PH-AppB

 

DC1

3/18

Boolean Algebra, Gates

M-Ch2, PH-AppB

 

DC1

3/23

Simplif. with K-Maps I

M-Ch3,

 

DC2

3/25

Simplif. with K-Maps II

M-Ch3

 

DC2

3/30

 Spring Break

 

 

 

4/1

Spring Break

 

 

 

4/6

Encoders, Decoders,Mux

M-Ch4

A4 out

DC3

4/8

Arithmetic Circuits

M-Ch4

 

DC4

4/13

Sequential Circuits I

M-Ch.5

 

DC5

4/15

Sequential Circuits II

M-Ch5

 

Dc5

4/20

Registers and Counters

M-Ch6

A4 due, A5 out

DC5

4/22

State Machines Analysis I

M-Ch5

 

DC6

4/27

State Machines AnalysisII

M-Ch5

 

DC6

4/29

State Mach. Design I

M-Ch5

 

Dc6

5/4

State Mach. Design II

M-Ch5

 

Dc6

5/6

MIPS Processor, Wrap-up and Review

PH-Ch5

A5 due

MIPS13