CS231 Spring 2004  

DESIGN OF A SIMPLE PROCESSOR (DATA PATH)

1. Purpose

The purpose of the project is to build a simple processor without a Control Unit that is 4-bits and can do various register transfer operations, ALU operations over a common bus.

See the bottom of the lab for the point breakdown, deadlines, and turn-in directions.

2. Background

2.1. ALU

Build a 4-bit  ALU that can do ADD, SUBTRACT, INCREMENT COMPLEMENT as arithmetic operations and AND, OR, XOR and NOR operations as logic operations.

2.2. The registers

You will build 4-bit  parallel-load registers from D flip flops as described in class.. Since we do not deal with memory in this lab, we will assume that the content of the registers is our output.

2.3. Decoder

The decoder will determine the destination register of any output from the ALU.

2.4. Multiplexers

Multiplexers are used to select between any registers or immediate data (0 or 4-bit data)  input to the ALU.

3. Preparation

Design and build the following circuits

  1. 3 X 4-bit register bank built from D flip flops. Each of these have a common clock and distinct input and output bits. Also a write enable input for each register exists. (provide ANDing of a common WEN input and the separate outputs of the decoder to provide separate write enables for each register)
  2. Multiplexers : These multiplexers are required to choose the operands to the ALU
  3. A 2:4 Decoder : Each output line from the decoder will enable one register (the write register) from the bank.

4. The Processor

Using all of the circuits above, build a simple processor as shown below:


Note: REG BANK is R0-R2 to give an extra input for immediate data to the right MUX ( and 0 to the left to enable loading a reg)

5. Operation description

 For this  datapath,  5 instructions are : MOV, ADD, AND, SUB and COMP.

If you look carefully at our CPU, inputs A, B, C and WEN help us manipulate MUXes, the ALU, and other components to perform certain things. Therefore, A, B, C, WEN (8 bits total) define the instruction. They make up an opcode of an instruction. Other inputs – D and Data – define the target register and the input data.

Theoretically, we can go on and define many more useful instructions in addition to MOV, ADD, AND, SUB and COMP, since we have A, B, C, WEN (8 bits total) to modify. Suppose we wrote some code using our instructions. Now, how do we convert our instructions into machine code that our CPU would understand? We need to assign a certain input combination to every instruction.

Your processor executes the instruction word (14 bits) as below:

Name

Size

Function in CPU

Programming function

A

13-12

Mux1 control

Defines Instruction

(this is the so-called op-code in MIPS)

B

11-10

Mux2 control

C

9-7

ALU control

WEN

6

Reg File Write Enable

D

5-4

Reg File Register Select

Defines the target

Data

3-0

Input Data (when necessary)

Input Data (when necessary)

 

So again, our task is to convert the instructions, which are easy for us to understand, into machine code, which our CPU can understand. Let’s take MOV R0, #3 for example.

What is the opcode for this instruction? Look at the CPU circuit. We have some input data in this instruction. This means that Mux2 needs to select Data[3..0],  So B, which controls it, should  be 11. B=11.

Then we need to take this data and send it to the register bank. So we just add 0 to it in the ALU. To do that, we need our Mux1 to select 0 (A=11), C=000.

We need to write to the registers. So we set WEN=1.

What register do we write to? R0. So input 00 into our decoder. (D=00).

Finally, our data is 310=00112. Therefore, Data=0011.

So we get an input combination that we can actually plug into Max Plus .scf file and test our circuit with:

A

B

C

WEN

D

Data

11

11

000

1

00

0011

As the result of this operations, we expect R0=0011.

Convert other instruction code into machine code using the same approach.

6. Test the following program :

(left operands are the destinations as in Intel processors)

  1. MOV R0, #3 R0 = 3
  2. MOV R1, #4 R1 = 4
  3. ADD R0, R1 R0 = 7
  4. MOV R2, R0 R2 = 7
  5. SUB R2, #2 R2 = 5
  6. AND R0, R1 R0 = 4
  7. COMP R0 R0 = 0xB (COMPlement R0)

and check the contents of the registers in each case.

Note:

    1. To load a value to a register add the value from right mux to 0 value from left and transfer it to destination via the decoder
    2. Providing a Write Enable to register file provides ease in write synchronization

7. Turn In, etc.

1. A Report describing your work with the circuits required

2. Convert the program in (6) into machine code.Hand  it with report

2. Design and test the CPU as described. Demo in class

The project counts as an extra assignment (6 %) .